High performance integrated circuits have traditionally been characterized by the clock frequency at which they operate. Gauging a circuit design's ability to operate at the specified frequency requires having the capability of measuring timing delays during the design process. Static timing analysis is a method of computing the expected process delays of a digital circuit without requiring circuit simulation.
Static timing analysis of sequential circuits requires the computation of the minimum and maximum delay requirements between every pair of source and destination registers that have a valid combinational path between them. These delay requirements depend on clock waveform characteristics feeding the registers. As such, delay requirements ultimately depend on the worst-case single cycle setup and hold time between pairs of clocks.
The worst-case single cycle setup time between a source clock and destination clock is defined as the smallest delay difference between the destination clock edge that latches the data, and the preceding source clock edge that launches the data. The base period is the minimum time after which two clock waveforms repeat and can determined by calculating the least common multiple (LCM) of the two clock periods.
The worst-case single cycle hold time is defined as the smallest non-negative difference between a source clock edge, and the destination clock edge that either precedes the source clock edge or occurs at the same time as the source clock edge. For clocks without a relative offset between them, the worst-case single cycle hold time is always zero.
Existing methods to determine the worst-case single cycle setup and hold times exhaustively check all valid setup and hold relationships across the base period of two clock periods. These methods require time proportional to the base period to determine these relationships. The amount of time spent to determine the worst-case setup and hold relationships for circuits with large base periods can be very large and can result in costly delays to completing a circuit design. Therefore, what is needed is a method to directly compute the worst-case single cycle setup and hold time without having to exhaustively check each valid setup and hold relationship combination.